Developing High-Speed LTE Applications

By Edward Young and Paul Moakes, CommAgility

Next generation networks based on LTE offer download speeds up to 100 Mbps per subscriber. Such high rates put increased stress on processor power for the radio interface and for I/O within the baseband processing system. Meanwhile, data is becoming the main traffic type, session lengths are increasing, and operators are under pressure to reduce costs.

Flexibility is a key here. Macro basestations will provide wide area coverage, but pico cells will fill in areas of poor coverage or high user density. Even as LTE is being rolled out today, operators want equipment which can be upgraded to LTE-Advanced inexpensively.

LTE systems create increased bandwidth demands. If we look at the Common Public Radio Interface (CPRI), until recently the standard supported only up to 2.5Gbps. For LTE, this is rarely fast enough, hence the standard has been extended to 9.8Gbps in the latest specification (version 4.2). Such high bandwidths stress system infrastructure.

How can the CPRI interface be implemented in practice? Although SoCs (Systems on Chip) are starting to incorporate CPRI interfaces, they are usually tailored to a particular solution. Clock synchronization inflexibility, evolving frame formats, and master-only support mean that most practical interfaces requires additional logic.

A more flexible approach is to use subsystems based around FPGAs, DSPs, or both. Changes in the CPRI standard or interface customization, for example the addition of security or new wireless standards, is then easy to accommodate.

Using a high-speed, low latency interconnect such as SRIO, a subsystem can include two multicore DSPs and an FPGA to handle baseband processing for one 10MHz sector of LTE. Increased bandwidth demands can be met by extending the network of processors across the backplane using SRIO.

End-to-end jitter and latency constraints become even tighter in LTE systems. Responding to this, RapidIO Gen2 introduces higher performance and a reduction in protocol overhead. It also provides for 5.0 and 6.25Gbaud rates with 8x and 16x link widths, raising the maximum link bandwidth to 80Gbps.

Beyond these concerns, designers also must identify the right solutions for media access, security, and network connectivity. Dedicated accelerators and configurable processors can both be considered. A complete LTE integration must also include provision for timing recovery.

LTE continues to provide many technical challenges to meet the increasing bandwidth demands of subscribers. At the same time, operators want to deploy solutions which can be adapted inexpensively to emerging standards such as LTE-Advanced. For such applications, basestation designers need scalability, flexibility, and the right level of processing power and I/O speed.

One approach is based around programmable DSPs and FPGAs, such as in the CommAgility AMC-2C6670 and AMC-2C6616. They provide advanced PHY layer processing capabilities using TI’s latest C66x fixed- and floating-point DSP family and Xilinx Virtex 6 FPGAs. RapidIO Gen2 interconnects and CPRI 10x external line rates to remote radio heads make the AMCs ideal for scalable LTE-Advanced basestations or test applications.

Programmable DSPs and FPGAs offer the flexibility required in today’s wireless systems. They can serve as a foundation for LTE and LTE-Advanced basestations.

Edward Young is Managing Director and Paul Moakes is Technical Director at CommAgility. You can reach them at Edward.young@commagility.com and paul.moakes@commagility.com, respectively.