Meeting the Growing Demands for Memory in Multicore Applications
By Paul Washkewicz, Inphi
Most current AdvancedTCA CPU boards have multicore processors with large amounts of memory. Large memory banks are essential to avoid bus conflicts in the multicore era and to support virtualization of applications and operating systems. Virtualization plays a key role in supporting multiple operating systems, providing security, and enabling many applications to run simultaneously. The combination of multicores with virtualization improves utilization and efficiency, but it also increases overall power consumption. In fact, memory has become the largest consumer of energy, particularly as manufacturers have made processors more energy-efficient.
Telecom equipment designers are seeking ways to increase the processing power of their servers without adding real estate, and without exacerbating power and cooling issues. But multicore architectures running multiple threads in virtual machines require more memory, and server memory capacity and performance are not scaling cost-effectively.
Currently, physical layers of memory controllers within server CPUs are constrained by limitations on their capacity and bandwidth. Exceeding those limits diminishes the integrity of the data transfer between the CPU and memory components. As server CPUs push to higher speeds, their ability to drive more memory actually decreases.
There are only a few ways to scale to higher memory density and higher bandwidth. The key challenge is that the memory controller must drive more modules and memory components, and therefore must handle higher loads on its buses. Current generations of memory controllers can drive up to three memory slots per channel. There is a tradeoff between how fast the channel can run versus the number of modules installed, because more modules require the controller to drive longer trace lengths that increase electrical loading on its drivers. It then becomes difficult to achieve the timing and signal integrity needed to run high-performance applications.
Most memory-scaling schemes have been modifications of the popular dual-inline memory module (DIMM) architecture. For instance, the registered DIMM (RDIMM) offers higher memory capacities and bandwidth than an un-buffered DIMM (UDIMM). The RDIMM uses a register to “buffer” command and address signals that traverse the DIMM. However, the performance of RDIMMs is reaching its limits.
Inphi has recently introduced a solution to the memory dilemma by developing an interface technology that enables servers to take full advantage of multicore and virtualization technologies and improve memory scaling, power consumption, and total cost of ownership. Inphi’s Isolation Memory Buffer (iMB™) technology and iMB01 component are driving the creation of a new class of memory modules -- load-reduced, dual-inline DIMMs (LRDIMM) – capable of delivering up to four times the memory capacity and nearly double the bandwidth.
New memory technology offers a compelling approach that solves serious challenges for multicore-based AdvancedTCA processor boards. The Isolation Memory Buffer approach works in the current generation of DDR3-based systems, while the scalability of the technology ensures a long life and continued application for future DDR3 and DDR4-based systems.
Paul Washkewicz is Vice President, Server and Storage Products, at Inphi. You can reach him at pwashke@inphi.com.