RapidIO Trade Association Defines Gen 3 Specification Update

By Tom Cox, RapidIO Trade Association

The RapidIO® Trade Association has formed a technical task group to define the 3.0 version of its specification. The main goals are to enable additional high speed link implementations and broaden market applications. The new specification, officially Serial RapidIO Gen 3, will be fully backwards compatible with Gen 2. 

The 3.0 PHY Task Group is developing a higher performance PHY for the RapidIO serial protocol with the following characteristics:

• Data rate per lane of at least 8 Gbps
• Asymmetric link operation
• Power efficient
• Low latency
• Fault tolerant
• Bit error rate below 10-12

In addition to the Gen 2 Specification, the RapidIO Trade Association has developed an updated Gen 2 Bus Functional Model (BFM). The BFM provides interoperability and compliance checking, is supplied as a modular behavioral C model, and provides a set of features and functions for simulating and verifying RapidIO systems of arbitrary complexity. The BFM is available to RapidIO Trade Association members in source code or object code form and is designed as a flexible tool for the development, evaluation and verification of RapidIO interface products. For more information visit www.rapidio.org/education/documents/RTA_BFM_documentation.pdf.

Technology Roadmap
The RapidIO Trade Association has a technology roadmap that provides details about RapidIO Specification Gen 2, and previews the development of Specification Gen 3, which will continue to be defined collaboratively over the next 12 months. While the current standard (Specification Rev. 1.3) will continue to dominate embedded applications for the foreseeable future, silicon using the latest revision is expected to debut in 2010. The embedded systems market has a stable and longer lifecycle then PC and Consumer markets, the needs of this market are reflected in the collaborative efforts of the association’s members to develop the appropriate technology, cost and performance in a timeframe suitable for the needs of its members. Details can be found at http://www.rapidio.org/education/Roadmap/.

RapidIO is an established, scalable, open-standard, switched fabric, designed by the leaders in embedded computing specifically for OEMs building equipment in the wireless infrastructure, edge networking, storage, scientific, military and industrial markets. RapidIO delivers the reliability, cost effectiveness, performance and scalability required in these markets. RapidIO also supports a roadmap which is attuned to the changes affecting designers of embedded infrastructure. Additional details can be found on www.RapidIO.org

Tom Cox is Executive Director of the RapidIO Trade Association. You can reach him at tom.cox@rapidio.org. RapidIO is a trademark of the RapidIO Trade Association.